PCIe I/O Virtualization Public Training Course

Description

Multi core processors and the advances in processor virtualization technology are making new demands on the I/O subsystems that form the heart of any computer system today. PCI Express (PCIe) is the next generation of the PCI/PCI-X specification and provides a significant increase in I/O system throughputs beyond that provided by PCI/PCI-X. In order move PCIe beyond a simple local I/O component interconnect the PCI-SIG has introduced three new specifications: Single-root (SR-IOV); Multiple-root IOV (MR-IOV); and Address Translation that address I/O virtualization. In Dashcourses 3-day PCIe IOV course will cover the basic principles and key highlights of version 1.0 of the Address Translations Services specification, and of versions 1.0 of the SR-IOV and MR-IOV specifications.

Objectives

• Provide an overview of Intel and AMD’s virtualization technologies
• Gain an understand the new terminology associated PCIe IOV
• Learn how Single Root and Multi Root IOV build on the standard PCI Express specification and what additional functions are introduced to cater for these new capabilities
• Learn what Address Translation Services is about and how it is used
• Learn the requirements and intended usage of SR IOV
• Cover the key aspects of MR IOV

Prerequisites

Students are expected to be fully conversant with the topics introduced in Dashcourses PCI/PCI-X and PCI Express courses including PCI Express version 2.

Who Should Attend

This three day course is designed to provide a detailed understanding of the PCI Express IOV technology as it relates to board, platform, and system design issues as well as to BIOS, device driver and application programming, and test and de-bug issues. It is appropriate for design, debug, validation and field engineers and managers who need a good understanding of the hardware/software capabilities and the disciplines required for the successful introduction and support of PCI Express IOV in devices or systems.

Outline:

PCIe and Virtualization Review

• PCIe architectural components

• Device
• Switch
• Root Complex
• System
• Serial interconnect, topologies and fabrics
• Protocol Stack
• Configuration space
• Virtualization technologies
• CPU, platform, and hypervisor
• Intel VT

• X86 addressing and page tables
• Virtual Machine Extension instruction set
• Modes of operation
• AMD
• Direct Connect Architecture
• Rapid Virtualization Indexing
• Integrated Memory Controller
• Tagged Translation Look-Aside Buffer
• Device Exclusion Vector
• IOMMU
• Virtualization Benefits
• Desktop/workstation
• Servers

PCIe IOV Virtualization Overview

• Address Translation Services
• Single-Root
• Multi-Root
• System usage of PCIe IOV

• Benefits
• Examples

SR IOV and Address Translation Services

• Single-Root topologies

• Architectural Overview

• PFs and VFs
• Topologies
• Benefits and usage of ATS
• Existing methods
• PCIe methods
• System benefits
• ATS and SR IOV
• SR IOV details
• PCI interoperability
• SR-IOV Resource Discovery
• New TLPs
• Reset Mechanisms
• IOV Re-Initialization and Reallocation
• VF Migration
• Configuration
• SR-IOV Extended Capability
• Error Handling
• Interrupts
• Interrupt Mechanisms
• Power Management
• PV/VF Power Management States
• Link Power Management State
• VF Power Management Capability
• Translation Services details
• Memory Request with Address Type
• Translation Requests
• Translation Completion
• Completions with Multiple Translations
• Invalidation
• Invalidate Request
• Invalidate Completion
• Semantics and Acceptance Rules
• Flow Control and Ordering Semantics
• Implicit Events
• Configuration
• ATS Capability Structure

Multi-Root Topologies

• Architectural Overview

• How does MR-IOV work
• MR Transaction Layer
• MR Protocol Changes
• MR Link Protocol Negotiations
• TLP Prefix Tagging
• MR Topology Initialization
• MR Device Initialization
• Configuration
• Device MR-IOV Extended Capability
• Switch Configuration Space
• Switch MR-IOV Extended Capability