PCI/PCI-X Architecture Training Course | | Course Length - 3 Days | | | | Course Description PCI and PCI-X have become defacto industry standards for defining local I/O expansion for PC and computing platforms and can be found on PCs, servers, I/O subsystems and in embedded designs. This three-day PCI Architecture training course provides a detailed guide to these PCI specifications and covers all aspects of PCI 3.0 and PCI-X 2.0 for hardware and software design including PCI transaction principles, hardware handshake requirements with timing examples, error detection and handling, and electrical issues and device configuration. 32-bit and 64-bit busses will be covered as well as bus frequency options. | | | | | Course Objectives: - Understand the benefits of PCI/PCI-X as used in today’s computing systems
- Learn the bus protocol for PCI/PCI-X, bus signals and functions, and PCI-X registered bus concept
- Learn PCI/PCI-X command set, timing transaction details and the effects on single and multiple PCI bus systems
- Explore PCI arbitration, bus latency and delay issues and system performance issues
- Learn PCI configuration space, discovery and initialization requirements, including the PCI-X register set
- Re-enforce concepts through interactive workshops
- Gain an understanding of ROM BIOS, PCI bridge, Hot-Swap and COMPACT PCI
| | | | | | Who Should Attend? This course is intended for hardware and software design and test engineers who work with the PCI bus as well as project engineers responsible for overseeing or troubleshooting systems that contain PCI devices. This course or equivalent experience is required prior to taking the PCI Express Architecture courses. | | | | | | Workshops Workshops will be placed throughout the course to emphasis practical parts of the specification and include: - Transaction Timing
- Interrupts
- Bus/Device Address Enumeration
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